Magnus Jahre

Førsteamanuensis

Institutt for datateknologi og informatikk Fakultet for informasjonsteknologi og elektroteknikk

magnus.jahre@ntnu.no 73593680 95222309

IT-bygget, 404, Gløshaugen, Sem Sælands vei 9

Mine interesser er minnesystemer for flerkjerneprosessorer, heterogene systemer, simulering av datamaskinarkitekturer, energieffektivitet og kompilatorteknikk.

Gå til den engelske siden for mer informasjon om min forsknings- og undervisningsaktivitet.

Vitenskapelig, faglig og kunstnerisk arbeid

Viser et utvalg av aktivitet. Se alle publikasjoner i databasen

2020

Zhao, Xia; Jahre, Magnus; Eeckhout, Lieven. (2020) HSM: A Hybrid Slowdown Model for Multitasking GPUs. ASPLOS'20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems.

2019

Koraei, Mostafa; Fatemi, Omid; Jahre, Magnus. (2019) DCMI: A Scalable Strategy for Accelerating Iterative Stencil Loops on FPGAs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 16 (4).
Wang, Lu; Jahre, Magnus; Adileh, Almutaz; Wang, Zhiying; Eeckhout, Lieven. (2019) Modeling Emerging Memory-Divergent GPU Applications. IEEE computer architecture letters. vol. 18 (2).

2018

Jahre, Magnus; Eeckhout, Lieven. (2018) GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime. IEEE Symposium on High-Performance Computer Architecture (HPCA). vol. 2018-February.
Yuxi, Liu; Zhao, Xia; Jahre, Magnus; Wang, Zhenlin; Wang, Xiaolin; Lou, Yingwei; Eeckhout, Lieven. (2018) Get Out of the Valley: Power-Efficient Address Mapping for GPUs. International Symposium on Computer Architecture.

2017

Umuroglu, Yaman; Fraser, Nicholas J.; Gambardella, Giulio; Blott, Michaela; Leong, Philip W.; Jahre, Magnus; Vissers, Kees. (2017) FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.

2016

Reissmann, Nico; Falch, Thomas Løfsgaard; Bjørnseth, Benjamin Andreassen; Bahmann, Helge; Meyer, Jan Christian; Jahre, Magnus. (2016) Efficient control flow restructuring for GPUs. International Conference on High Performance Computing & Simulation (HPCS).
Umuroglu, Yaman; Jahre, Magnus. (2016) Random access schemes for efficient FPGA SpMV acceleration. Microprocessors and microsystems. vol. 47B.

2015

Bahmann, Helge; Reissmann, Nico; Jahre, Magnus; Meyer, Jan Christian. (2015) Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 11 (4).
Cebrian, Juan; Jahre, Magnus; Natvig, Lasse. (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing. vol. 97 (11).
Umuroglu, Yaman; Morrison, Donn; Jahre, Magnus. (2015) Hybrid Breadth-First Search on a Single-Chip FPGA-CPU Heterogeneous Platform. 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015.

2014

Cebrian, Juan; Jahre, Magnus; Natvig, Lasse. (2014) Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks. IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.
Jahre, Magnus. (2014) Graph-based Performance Accounting for Chip Multiprocessor Memory Systems. Proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT).
Umuroglu, Yaman; Jahre, Magnus. (2014) An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators. 2014 32nd IEEE International Conference on Computer Design (ICCD).

2010

Grannæs, Marius; Jahre, Magnus; Natvig, Lasse. (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science (LNCS). vol. 5 (1).
Jahre, Magnus; Grannæs, Marius; Natvig, Lasse. (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science (LNCS).

2009

Jahre, Magnus; Grannæs, Marius; Natvig, Lasse. (2009) A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. 11th IEEE International Conference on High Performance Computing and Communications (HPCC 2009).
Jahre, Magnus; Natvig, Lasse. (2009) A Light-Weight Fairness Mechanism for Chip Multiprocessor Memory Systems. Proceedings of the 6th ACM Conference on Computing Frontiers.