Bakgrunn og aktiviteter
Trond Ytterdal received his M.Sc. and Ph.D. degrees in electrical engineering from the Norwegian Institute of Technology in 1990 and 1995, respectively. He was employed as a research associate at the Department of Electrical Engineering, University of Virginia (1995-1996) and as a research scientist at the Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute in Troy, New York (1996-1997). From 1997 to 2001 he worked as a senior ASIC designer at Nordic Semiconductor in Trondheim, Norway. Since 2001 he has been on the faculty of the Norwegian University of Science and Technology (NTNU), where he is a Professor at the Department of Electronics and Telecommunications. Prof. Ytterdal's present research interests include design of analog integrated circuits, behavioral modeling and simulation of mixed-signal systems, modeling of nanoscale transistors and novel device structures for application in circuit simulators. He has authored and co-authored more than 200 scientific papers in international journals and conference proceedings. He is a co-author of the books Semiconductor Device Modeling for VLSI (Prentice Hall, 1993), Introduction to Device Modeling and Circuit Simulation (Wiley, 1998) and Device Modeling for Analog and RF CMOS Circuit Design (Wiley, 2003), and has been a contributor to several other books published internationally. He is also a co-developer of the circuit simulator AIM-Spice. Prof. Ytterdal is a member of The Norwegian Academy of Technological Sciences and a Senior Member of IEEE.
Vitenskapelig, faglig og kunstnerisk arbeid
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- (2018) Tunnel FET Analog Benchmarking and Circuit Design. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.
- (2018) A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology. Integration.
- (2017) A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging. IEEE Transactions on Biomedical Circuits and Systems. vol. 11 (5).
- (2017) An in-probe low-noise low-power variable-gain receive amplifier for medical ultrasound imaging using CMUT transducers. Analog Integrated Circuits and Signal Processing.
- (2017) An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation. Proceedings of the IEEE Custom Integrated Circuits Conference. vol. 2017-April.
- (2017) Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems. vol. 48.
- (2017) Ultra-Low Voltage and Energy Efficient Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Microprocessors and microsystems. vol. 56.
- (2017) A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers. IEEE Journal of Solid-State Circuits. vol. 52 (7).
- (2016) Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array. Microelectronics Journal. vol. 48.
- (2016) Noise transfer functions and loop filters especially suited for noise-shaping SAR ADCs. Proceedings - IEEE International Symposium on Cicuits and Systems. vol. 2016-July.
- (2016) A 1 MHz BW 34.2 fJ/step continuous time delta sigma modulator with an integrated mixer for cardiac ultrasound. IEEE Transactions on Biomedical Circuits and Systems. vol. 11 (1).
- (2016) Universal charge-conserving TFET SPICE model incorporating gate current and noise. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. vol. 2.
- (2016) Steep slope transistors: Tunnel FETs and beyond. Proceedings of the European Solid-State Circuits Conference, IEEE. vol. 2016-October.
- (2016) Low-power low-area beamformer design using switched-current ARAM using external capacitors. Microelectronics Journal. vol. 48 (2).
- (2016) A 54-uW Inverter-Based Low-Noise Single-Ended to Differential VGA for Second Harmonic Ultrasound Probes in 65-nm CMOS. IEEE Transactions on Circuits and Systems - II - Express Briefs. vol. 63 (7).
- (2016) Low noise, -50 dB second harmonic distortion single-ended to differential switched-capacitive variable gain amplifier for ultrasound imaging. IET Circuits, Devices & Systems. vol. 10 (3).
- (2016) A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOI. Proceedings of ESSCIRC. vol. 2016-October.
- (2016) An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS. Analog Integrated Circuits and Signal Processing. vol. 90 (1).
- (2015) Modelling effect of parasitics in plasmonic FETs. Solid-State Electronics. vol. 104.
- (2015) HD2 reduction technique for single-ended amplifier. Electronics Letters. vol. 51 (25).