Bakgrunn og aktiviteter
Trond Ytterdal received his M.Sc. and Ph.D. degrees in electrical engineering from the Norwegian Institute of Technology in 1990 and 1995, respectively. He was employed as a research associate at the Department of Electrical Engineering, University of Virginia (1995-1996) and as a research scientist at the Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute in Troy, New York (1996-1997). From 1997 to 2001 he worked as a senior ASIC designer at Nordic Semiconductor in Trondheim, Norway. Since 2001 he has been on the faculty of the Norwegian University of Science and Technology (NTNU), where he is a Professor at the Department of Electronics and Telecommunications. Prof. Ytterdal's present research interests include design of analog integrated circuits, behavioral modeling and simulation of mixed-signal systems, modeling of nanoscale transistors and novel device structures for application in circuit simulators. He has authored and co-authored more than 200 scientific papers in international journals and conference proceedings. He is a co-author of the books Semiconductor Device Modeling for VLSI (Prentice Hall, 1993), Introduction to Device Modeling and Circuit Simulation (Wiley, 1998) and Device Modeling for Analog and RF CMOS Circuit Design (Wiley, 2003), and has been a contributor to several other books published internationally. He is also a co-developer of the circuit simulator AIM-Spice. Prof. Ytterdal is a member of The Norwegian Academy of Technological Sciences and a Senior Member of IEEE.
Vitenskapelig, faglig og kunstnerisk arbeid
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- (2020) High Speed Terahertz Devices via Emerging Hybrid GNRFET/Josephson Junction Technologies. IEEE transactions on applied superconductivity. vol. 30 (8).
- (2020) A Low-power and Low-noise Multi-purpose Chopper Amplifier with High CMRR and PSRR. IEEE Engineering in Medicine and Biology Society. Conference Proceedings. vol. 2020-.
- (2020) A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes. Analog Integrated Circuits and Signal Processing.
- (2020) Impedance and Noise of Passive and Active Dry EEG Electrodes: A Review. IEEE Sensors Journal.
- (2020) Plasmonic FET Terahertz Spectrometer. IEEE Access. vol. 8 (3).
- (2020) TeraFET Optimization for 0.1 THz to 10 THz Operation. Radio Science Bulletin. vol. 2.
- (2020) An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. IEEE Transactions on Circuits and Systems - II - Express Briefs.
- (2020) Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. IEEE Transactions on Very Large Scale Integration (vlsi) Systems. vol. 28 (10).
- (2020) Carbon Nanotube Metal Polymer Composites for Flexible Active Interconnects. ECS Transactions. vol. 97 (7).
- (2020) Carbon Nanotube Detectors and Spectrometers for Terahertz Range. Crystals. vol. 10 (7).
- (2020) Percolation Carbon Nanotube Thin Film Transistors. ECS Transactions.
- (2019) Leakage Current and Static Power analysis of TFET 8T-SRAM Cell. Materials Today: Proceedings. vol. 7 (3).
- (2019) A high-voltage cascode-connected three-level pulse-generator for bio-medical ultrasound applications. IEEE International Symposium on Circuits and Systems proceedings.
- (2019) Compact Terahertz SPICE/ADS Model. IEEE Transactions on Electron Devices. vol. 66 (6).
- (2019) High Speed High Sensitive Temperature Sensing Integrated Devices for a Wide Temperature Range Operation Using TFET Devices. International Journal of Advances in Electronics and Computer Science. vol. 6 (2).
- (2019) GNRFET Analog Devices For Optimum Noise Performance and High Frequency Stability. International Journal of Advances in Electronics and Computer Science. vol. 6 (2).
- (2019) Low power-high speed performance of 8T static RAM cell within GaN TFET, FinFET, and GNRFET technologies – A review. Solid-State Electronics. vol. 163 (1).
- (2018) Compact Terahertz SPICE Model: Effects of Drude Inductance and Leakage. IEEE Transactions on Electron Devices. vol. 65 (12).
- (2018) Tunnel FET analog benchmarking and circuit design. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC). vol. 4.
- (2018) A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology. Integration. vol. 63.